Electrostatic discharge (ESD) in semiconductor integrated circuits (IC's) is a well-known problem. The inadvertent presence of a sudden voltage spike in an IC can cause physical destruction of IC features. For example, ESD-induced spikes can rupture the thin gate oxide of a field effect transistor (FET), or simply degrade the p-n junction of a semiconductor device, effectively destroying proper IC operation.
There are three basic models for simulating the effects of ESD events on semiconductor devices: the human body model, the machine model, and the charged device model. These models can be used to construct testers to quantify the resistance of devices to ESD events, and to model the effectiveness of a proposed ESD protection circuit using standard circuit simulation techniques.
The human body model is intended to simulate the effect of human handling on semiconductor devices. In FIG. 1, the capacitance C1 simulates the capacitance of the human body and is generally chosen to be 100 pf. The resistance R1 simulates the series resistance of the human body and is usually modeled as 1.5 K.OMEGA.. The capacitor C1 is charged to an initial voltage V1 and then discharged into the device under test (DUT). Devices which can withstand precharge voltages on the order of 2 to 3 Kev are considered acceptable by industry standards. A widely followed standard for testing according to the human body model is presented in MIL-STD-883C, notice 8, method 3015.7, "Electrical Discharge Sensitivity Test" (1989).
The machine model or "zero ohms" model utilizes the circuit of FIG. 1, except that C1 is 200 pf and R1 approximates "zero ohms." In a practical construction, R1 is in the range of 20 to 40 ohms. The discharge time constant of the machine model is much less than the human body model, and parasitic circuit components have more influence over the maximum current and voltage seen by the DUT during the discharge. A device that can withstand 400 volts is considered acceptable by industry standards. This model is commonly used in Japan and is covered in EIAJ Standards of the Electronic Industries association of Japan,, IC-121 Book 2 (1988).
The charged device model is used to simulate the ESD failure mechanisms associated with machine handling during the packaging and test of semiconductor devices. According to this model, an IC package is charged to a potential (100 volts to 2000 volts) by triboelectricity or by the presence of large electric fields. Then, the device is discharged to ground via any of the device pins. The charging is normally done via the substrate pin and the discharge is initiated by touching a device pin with a grounded low inductance probe. The time constant for this discharge process is less than 150 ps, and the discharged energy depends on the package capacitance.
A conventional input protection network is illustrated in FIG. 2. When the polarity of the ESD stress is negative with respect to ground, diode D2 becomes forward biased. As long as the diode series resistance is low enough, voltages seen by the circuit remain low enough to minimize on chip power dissipation and protect the CMOS gate oxide. For example, the human body model charged to 3 KeV corresponds to an instantaneous current of 2 amps. Therefore, the diode series resistance should be no more than 4 ohms in order to keep total voltage seen by the circuit to 8 volts, corresponding to the worst case breakdown for a 10 nm gate oxide typical of a 0.5 .mu.m CMOS process.
When the ESD stress is positive with respect to ground, there are two possibilities for current flow. First, diode D2 charges up until it reaches reverse breakdown, at which point the rise in voltage at the input tends to be clamped. Unfortunately, the reverse breakdown for D2 may be higher than the gate oxide breakdown, thus allowing voltages damaging to input or output device buffers to pass. Second, diode D1 becomes forward biased and begins to charge up Vcc until some breakdown mechanism on the die, such as parasitic field turn-on, gate oxide breakdown, or latchup, clamps the rise in Vcc. It is this mechanism that causes failures internal to the die during ESD stress.
A problem with conventional ESD solutions is that many IC's require inputs to be at voltage levels well above the positive supply voltage or below ground potential. The conventional solutions clamp the input voltage at a diode drop above Vcc or below ground. Clearly this is unacceptable when the magnitude of the input voltage is above Vcc or below ground. Thus, it is desirable to have an ESD protection circuit that is able to dissipate ESD stress from such inputs.